FIG. 24 illustrates an example embodiment of the so-called split computer. As shown in FIG. 24, the remote target room 185 contains a number of targets having CPUs, hard drives, etc. One target 186 is shown connected to a work station 188 via a communications line 187 (illustrated as twisted pair). The target 186 is also referred to as the host side 186 and the work station 188 is also referred to as the remote side 188. On the host side 186, the CPU 189 communicates on a host bus 190. The host bus 190 can be a standard PCI bus within a CPU motherboard, or can be any other type of computer data bus. On the remote side 188, a remote bus 193 communicates with various local controllers 194 which will be described later in greater detail. Among other functions, the local controllers 194 support various peripherals 195 located at the work station 188. As one can see from FIG. 24, in effect, the bus that would ordinarily carry communications from CPU 189 to controllers 194 has been “split” into buses 190 and 193 communicating with each other via interfacing 191 and 192 and a communications line 187 such as twisted pair (or other communications media).
The practical result of the split computer is that the host bus 190 and remote bus 193 must be interfaced such that the CPU 189 can engage in normal communications with the local controllers 194. Ideally, the host bus 190 and remote bus 193 will be capable of communications along a large range of distances including a few feet, as far as one corner of a building to another, and even greater distances if necessary. The present invention is not limited to any particular type of communications line 187 (such as wire line, twisted pair (shielded and unshielded), fiber optic, air wave, etc.), but it would be particularly advantageous if the present invention allowed the host bus 190 to communicate with the remote bus 193 over long distances and/or via a packet-switched communications network. For this purpose, special interfacing 191 and 192 must be provided between the host bus 190 and remote bus 193 at the host side 186 and remote side 188.
Some schemes already exist for communication along a computer bus and between plural computer buses. Examples of these prior art interfaces are shown and described with respect to FIGS. 1-3. Thus, as shown in FIG. 2, a PCI type bus 12 may include a number of components communicating along the bus 12 in accordance with the standard PCI local bus specifications. The PCI local bus specifications are standards by which computer communications can occur within internal buses of a PC-based computer. The PCI local bus specification rev. 2.1, dated Jun. 1, 1995, is an example prior art PCI bus specification and is incorporated herein by reference. In FIG. 2, the PCI bus 12 provides communication between a master 14 and one or more targets 15A-15B. Communications occur when the master 14 provides information addressed to a particular targets 15A-15B and places that communication on the PCI bus 12. Such communications along PCI buses 12 are not uncommon.
The timing of communications between a master 14 and targets 15A-15B is traditionally specified in the bus specification. Thus, the PCI bus specification or PCI bus 12 provides hard limits on how much time can elapse before a command issued by master 14 “times out” without receiving response. In other words, master 14 may send a command to targets 15A-15B on PCI bus 12 with an address for target 15A to perform a particular operation. The target 15A must receive the command and respond to the command within a certain time set by the PCI standard before the master 14 will time out on the issued command.
Thus, as shown in FIG. 2, master 14 issues a command at clock C0 to target 15B. Target 15B will operate on the command and return a response (or acknowledgment) to master 14, which will be received by master 14 no later than C0+X where X is a number of clocks dictated by the bus standard. If C0+X exceeds the PCI standard for response time to a command, master 14 will time out on the command before it receives its response from target 15B. This situation is rarely, if ever, a design constant for a typical PCI system but it does limit the physical size of a PCI bus and has application to the present invention, as will be described.
The time out aspects of bus communications pose a problem in the split computer paradigm. Referring again to FIG. 24, assuming CPU 189 to be a client speaking on host bus 190, the CPU 189 will be sending commands to local controller 194 via the path (in order): host bus 190, interface 191, twisted pair 187, interface 192, and remote bus 193. Unfortunately, this distance of travel precludes the local controller 194 from operating on the command and responding to the CPU 189 in time before the CPU 189 times out on the command. In other words, the standard bus time out restrictions are too small for transmission response to occur from CPU 189 to local controllers 194 and back to CPU 189 before the time out occurs.
FIG. 1 illustrates a prior art arrangement which addresses communication between plural PCI buses 12 and 13. In the embodiment of FIG. 1, bridge 10 allows an increased number of masters/targets on a PCI system by connecting a first bus with a second bus to provide a second set of loads. The bridge 10 is a known device and may be, for example, a Digital Semiconductor PCI-to-PCI bridge. An example of such a bridge is the Digital Semiconductor 21152 bridge, described in Digital Semiconductor's February 1996 data sheet, which is incorporated herein by reference.
As shown in FIG. 3, the bridge 10 assists the clients 14/16 and targets 15A-B/17A-B to communicate with each other over the PCI buses 12 and 13. Thus, a master 14 communicates differently to targets 15A-B than it would to targets 17A-B. In the former case, if master 14 desires to read a memory location of target 15A, master 14 simply sends an address to target 15A on PCI bus 12 and target 15A acknowledges the request to master 14 on the PCI bus 12, before the time out condition occurs (and can then return the data). In the latter case, however, the target 17A cannot receive and return the information requested before master 14 will time out. Thus, the master 14 sends its read request to bridge 10 on PCI bus 12. The bridge returns an instruction to master 14 instructing the master 14 in essence “sorry, try again later.” Meanwhile, however, bridge 10 sends the read request to the target 17A on PCI bus 13. As the master 14 continues asking the bridge 10 for the read request and the bridge 10 continues to tell the master 14 “try again,” the target 17A is retrieving the requested data from its memory. Once the target 17A has retrieved the requested data, it puts it on PCI bus 13 to bridge 10. In the next instance in which master 14 sends the read request to bridge 10, the bridge 10 responds within the time out period with the requested information previously sent to it by the target 17A.
The prior art arrangement of FIG. 3 cannot be simply substituted into the split computer environment, however, since there are still time and distance restrictions on the bridge 10. The distance between the master 14 and bridge 10 cannot be so long that the client will time out on its command before it receives the “not yet” response from the bridge 10. Thus, the distance between master M and bridge 10 (FIG. 1) is limited by the bus standards and by normal propagation delays, as is the distance between bridge 10 and target S.
Thus, the solution to the split computer distance communications of FIG. 24 is not so simple as replacing the interfacing 191 and 192 with bridge 10 since that substitution will not yield satisfactory distances between the remote target room 185 (i.e., host side 186) and the work station 188. The present invention increases the distance between host side 186 and remote side 188 by essentially taking time out of the computer bus transmission factors. In other words, with the present invention, instead of a client timing out while data travels, the only significant time constraint in getting data from a target to a master (after a master commands the target) is the number of times a master will ask the target for data before it stops requesting. With the present invention, time out conditions should not occur as a result of responses to a command arriving too late.
In accordance with an example embodiment of the present invention, communications received from a bridge (as non-packet data) are packetized and communicated between specialized circuits (e.g., field programmable gate arrays and/or ASICs) and delivered to a second bridge for communication onto a remote computer bus (again as un-packeted data).